1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a process for detecting and screening weak cells of a semiconductor memory device.
2. Description of the Related Art
Each memory cell of a semiconductor memory device, such as a dynamic random access memory (DRAM) device, generally includes a transistor that functions as a switch and a capacitor that stores charges, which represent data. Whether data is in a ‘high’ level, which is logic ‘1’, or a ‘low’ level, which is logic ‘0’, is decided based on whether or not there are charges in the capacitor of a memory cell, that is, whether the terminal voltage of the capacitor is high or low.
The retention of data signifies a state that charges are accumulated in a capacitor. Theoretically, power is not consumed in this state. However, since the initial amount of charges stored in a capacitor may disappear due to leakage current caused by a PN bond of a metal-oxide semiconductor (MOS) transistor, the data stored in the capacitor may be lost. To protect the data from being lost, the data of the memory cell has to be read before the data gets lost to produce read information, and then the capacitor has to be re-charged according to the read information to keep the initial amount of charges. This operation has to be performed periodically to retain the data, which is called a ‘refresh operation.’
The refresh operation is performed whenever a refresh command is inputted into a memory device from a memory controller. The memory controller inputs a refresh command to the memory device whenever a predetermined time passes in consideration of a data retention time of the memory device. For example, when the data retention time of a memory device is approximately 64 ms and all the memory cells of the memory device may be refreshed only after the refresh command is inputted approximately 8000 times, the memory controller inputs the refresh command to the memory device approximately 8000 times within approximately 64 ms.
Furthermore, when the data retention time of some memory cells included in a memory device does not exceed a predetermined reference time during the process of testing the memory device, the memory device including such memory cells is regarded as a failed memory device and then abandoned.
When the memory device including the memory cells whose data retention time is shorter than the predetermined reference time, which are called ‘weak cells,’ is abandoned, a problem with the yield being deteriorated may arise. Additionally, even though a memory device passes the test, when weak cells occur at a later time, errors may occur in the memory device.
Moreover, since more than tens of millions of memory cells are integrated in a high density in one chip, the weak cells are more likely to appear despite advancements in the fabrication process. If an accurate test is not performed for the weak cells, the reliability of the memory device is damaged.
For this reason, researchers and the industry are developing diverse processes for detecting and screening weak cells.